(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of depositing a copper layer for dual damascene interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Damascene technology is an important capability in the present art of semiconductor manufacturing. The use of damascene and dual damascene schemes facilitates the use of copper for interconnects. Copper offers significant advantages due to its low resistivity when compared to aluminum.
Several approaches are currently available for depositing copper in integrated circuit manufacturing. First, the copper may be deposited by physical vapor deposition (PVD). PVD, or ionized PVD, processes benefit from available technology and relatively high throughput. However, PVD deposited copper has poor step coverage (less than 5%). Second, chemical vapor deposition (CVD) offers better step coverage than PVD. However, the deposited copper is not uniform in thickness. In addition, CVD requires the use of expensive materials called precursors to catalyze the reaction. Liquid precursors have difficult vaporization properties. Third, electroplating and electroless plating of copper are attractive alternatives to PVD and CVD because of lower equipment and material costs. However, plating methods require the presence of a seed layer to conduct or to catalyze the deposition reaction. This seed layer typically comprises copper, though other materials such as refractory metals have been suggested. When this seed layer is copper, it is typically deposited by a PVD process. In addition, electroless plating requires an induction layer as a catalytic surface and the use of reducing agents. Finally, plating processes can be very slow and dirty.
Referring now to FIG. 1, a cross-section of a partially completed prior art integrated circuit device is shown. A dual damascene trench has been formed using a conventional method. A semiconductor substrate 8 is shown. A dielectric layer 10, which may be a composite structure made up of several layers of dielectric material, is formed overlying the semiconductor substrate 8. Following the via and trench etch, a barrier layer 14 is formed overlying the opening. The barrier layer is comprised of a material that can prevent copper ion out-diffusion from the copper interconnect into the dielectric layer 10.
A copper plating process is intended for this prior art example. Therefore, a copper seed layer 18 is deposited overlying the barrier layer 14 by a physical vapor deposition process (PVD). Due to the limitations of PVD, however, the copper seed layer 18 does not cover the steps of the dual damascene trench adequately as shown by 22. The purpose of the present invention is to achieve a copper seed layer deposition process that is clean and conformal, meaning it has excellent step coverage, and does not require expensive precursors.
Several prior art approaches disclose methods to deposit metal layers in an integrated circuit device and related topics. In R. A. Kent et al, "Mass Spectrometric Studies at High Temperatures. IX. The Sublimation Pressure of Copper (II) Fluoride," The Journal of Physical Chemistry, Volume 70, number 3, March 1966, pp. 874-877, the authors attempt to measure the activation energy and the bond energy of CuF.sub.2. This bond is found to be very weak. The paper reports that sublimated CuF.sub.2 vapor reacts with tantalum at high temperature to produce solid copper and TaF.sub.5 gas. M. E. Gross et al., "Implications of dual damascene for electroplated copper interconnects," Solid State Technology, August 1999, pp. 47-52, focuses on the influence of damascene topology on the process of recrystallization of plated copper. This reference mentions the plating of copper onto a PVD copper seed layer overlying a PVD tantalum layer. U.S. Pat. No. 5,654,245 to Allen teaches a method to selectively metallize a semiconductor device. After forming apertures of a metal phobic layer into the support layer, a nucleating species is implanted. The nucleating species disclosed comprise molybdenum, tungsten, tantalum, and titanium. Copper is then selectively deposited by either metal-organic chemical vapor deposition (CVD), plasma-enhanced metal-organic CVD, or electroplating. U.S. Pat. No. 5,668,054 to Sun et al discloses a method to form a tantalum nitride diffusion barrier for use in a copper metalization scheme. The tantalum nitride is formed using a metal-organic CVD process. The copper layer is then formed overlying the tantalum nitride layer by either CVD or PVD. U.S. Pat. No. 5,350,484 to Gardner et al teaches a method to etch metals, including copper. Ions are implanted into the metal to improve etchability. For example, fluorine atoms may be implanted into copper. The resulting Cu.sub.x F.sub.y (copper Fluoride) can be etched using HCl, HF, H.sub.2 O, or mineral acid. U.S. Pat. No. 5,424,252 to Morishita discloses an electroless metal plating process that can be used to plate copper in a semiconductor device. Co-pending U.S. patent application Ser. No. 09/501968 (CS-99-159) to S. Gupta et al filed Feb. 10, 2000 teaches a method of depositing copper by disproportionation of simple Cu(I) ion to form an aqueous solution.